# PCIe - the High-Speed Internal Highway

USB isn't trying to be the fastest road in the building. Inside the case, a graphics card or an NVMe SSD
moves enormous amounts of data to and from the CPU and memory, *constantly*, with as little delay as
possible. That road is **PCIe** - the highway the serious hardware
bolts onto. Two ideas explain every slot, spec line, and "will this card run at full speed" question:
**lanes** and **generations**.

> ⏭️ This phase is about the *physical bus*. For the bigger picture of how the CPU, RAM, and these buses
> shuttle data between each other, see [How Data Moves Inside a Machine](/guides/how-data-moves-inside-a-machine).

## The mental model: PCIe is a highway measured in lanes

PCIe (PCI Express) is a bus - wires connecting expansion hardware to the rest of the system. Its defining
idea is the **lane**: one independent path for data, a tiny pair of wires for sending and another for
receiving, running at the same time (full-duplex). Many lanes can run *side by side* to the same device,
all carrying data in parallel.

📝 **Terminology.** The notation **x1, x4, x8, x16** ("by one," "by sixteen") = **how many lanes** a slot
or device uses. More lanes = more parallel paths = more total bandwidth.

It's a freeway: sixteen lanes (x16) move sixteen times what one lane (x1) does.

```text
   x1  ═                       1 lane   - a small device (Wi-Fi, sound card)
   x4  ════                    4 lanes  - typical NVMe SSD
   x8  ════════                8 lanes  - a second GPU, fast network card
   x16 ════════════════       16 lanes  - the main graphics card slot

   each "═" is one lane = one independent parallel path to the device.
   more lanes side by side = more total bandwidth at once.
```

Why this design exists: older expansion buses were *shared* - every card took turns on one common set of
wires, fighting for bandwidth. PCIe gives each device its own dedicated lanes straight toward the
system - a *point-to-point* connection, not a shared party line - so each device gets predictable,
private bandwidth.

## The slots on the motherboard

PCIe slots are the long connectors expansion cards push into, sized to match lane counts: a short slot
for x1, a long one for x16. A card's gold edge-connector ("the fingers") slides into a slot of matching
or larger size.

```text
   ┌─────────────────────────── MOTHERBOARD ───────────────────────────┐
   │                                                                    │
   │   [CPU]      ═══════════════ x16 slot ═══════════════  ← GPU       │
   │                                                                    │
   │             ════════ x4 slot ════════                ← NVMe/card   │
   │                                                                    │
   │             ══ x1 ══                                 ← Wi-Fi/sound │
   │                                                                    │
   │   (M.2 slots elsewhere on the board also run on PCIe lanes →NVMe)  │
   └────────────────────────────────────────────────────────────────────┘
```

A detail that trips people up: *physical* slot size and *electrical* lane count can differ -
"**x16 physical, x4 electrical**" means the slot is long enough for a big card but only four lanes are
actually wired. The card fits and works; it just gets four lanes, not sixteen. Manufacturers do this to
fit more long slots on a board than they have lanes to fully wire.

⚠️ **Gotcha - your card may be running at fewer lanes than you think.** A CPU and chipset only have so many
lanes to hand out. Populate several slots and M.2 drives at once and the board may quietly *reduce* lanes
to some of them - for example, dropping the main x16 GPU slot to x8 when a second card or certain M.2
slots are in use. The card still works, just on a narrower road than the slot's size implies. The
motherboard manual's lane-allocation table is the only reliable place this is spelled out.

## What plugs in here

PCIe is where the bandwidth-hungry hardware lives. The three you'll meet most:

- **Graphics cards (GPUs)** - the headline tenant of the x16 slot. They move massive amounts of data to
  and from the CPU and memory, which is exactly why they get the widest slot. (Their whole story is the
  [next phase](03-gpus-and-peripherals.md).)
- **NVMe SSDs** - fast storage on PCIe lanes (usually x4), typically through a small **M.2** slot.
  Talking directly to the PCIe highway instead of the older, slower disk interface is the entire reason
  NVMe is so much faster than older SSDs - full story in
  [Storage: HDD, SSD & NVMe](/guides/storage-hdd-ssd-nvme).
- **Network and other cards** - fast wired network adapters, Wi-Fi, sound, capture cards, add-in
  controllers. They need only a lane or two, so they live in the narrow x1/x4 slots.

## Why lane count *and* generation both matter

Bandwidth on PCIe is the product of **two** numbers. **Lane count** is the width of the road.
**Generation** is the speed of each lane: PCIe comes in numbered generations - Gen 3, Gen 4, Gen 5, and
so on - and each new generation roughly doubles the data rate *of a single lane*. A Gen 4 lane carries
about twice a Gen 3 lane, Gen 5 about twice Gen 4. (Doubling per generation is the consistent rule; the
exact rates are published by the spec.)

📝 **Terminology.** **Total bandwidth ≈ per-lane speed (generation) × number of lanes.**

The practical consequence: fewer fast lanes can equal more slow lanes. An x4 link on one generation
carries roughly what an x8 link carried on the generation before - same total, half the lanes. That's why
an NVMe drive on Gen 4 x4 can be genuinely fast despite "only" four lanes: each lane is moving a lot.

⚠️ **Gotcha - the connection runs at the *slower* end's terms.** PCIe negotiates down to whatever both
sides can do. Put a Gen 5 card in a Gen 3 slot and it works - at Gen 3 speeds. A card built for x16
dropped into an x8 link runs at x8. Nothing breaks and you usually get no error; you just silently get
less than the card is capable of. When a new GPU or SSD "feels slower than the reviews," a generation or
lane mismatch is a prime suspect - and most operating systems can report the link's actual negotiated
generation and width, so check rather than guess.

"Is this slot fast enough for this card?" is now two questions: enough *lanes*, and a recent enough
*generation*? And "why is my fast new drive not fast?" starts at the negotiated link.

## Recap

1. **PCIe is a point-to-point highway measured in lanes.** A lane is one independent parallel path; each
   device gets its own dedicated lanes instead of fighting for a shared bus.
2. **Slots are sized by lane count** - x1, x4, x8, x16 - but *physical* size and *electrical* lane count
   can differ ("x16 physical, x4 electrical"), and boards may reduce lanes when many slots are populated.
3. **GPUs, NVMe SSDs, and network/add-in cards** all plug in here; the bandwidth-hungry ones get the
   widest slots.
4. **Bandwidth = lane count × generation.** A newer generation can match more lanes of an older one, and
   the link always negotiates down to the slower end - silently capping cards that expected more.

Now to the headline tenant of that x16 slot: the GPU - what it's for, how it's fed, and how the everyday
peripherals from Phase 1 present themselves to the system.